Currently, remarkable progress is being made in technologies related to radio communication, and active research and development efforts are being made of small-sized ICs (Integrated Circuit) to be used in mobile phones. As one of ICs to be used mainly for mobile phones, a system-on-chip, in which an RF (Radio Frequency) circuit and a baseband circuit are mounted together on a single chip (hereinafter also referred to as hybrid integration) is now a focus of attention.
High-speed operation is needed for the RF circuit of the system-on-chip, and, miniaturization is also needed for the structure thereof. On the other hand, unlike the RF circuit, the baseband circuit need not be miniaturized. As is generally known, advanced miniaturization technology may lead to the problem that the cost of manufacture increases and the yield of manufacture decreases.
Incidentally, as is well known, transistors including an IC include a CMOS (Complementary MOS) transistor and a bipolar transistor. Since the gate voltage of the CMOS transistor is a low and the process steps thereof are easy to perform, the CMOS transistor is applied as an element of many types of ICs. On the other hand, the bipolar transistor is known to be more advantageous for high-speed operation than the CMOS transistor. Comparison between a bipolar transistor and a CMOS transistor both having the same microstructure shows that the bipolar transistor can achieve operating speed as high as that of a CMOS transistor of one or two generations ahead.
In consideration of the above-described viewpoint, it is desirable that the RF circuit of a system-on-chip should be composed of bipolar transistors advantageous for high-speed operation and the baseband circuit of the system-on-chip is composed of easy-to-manufacture CMOS transistors. A transistor which includes a bipolar transistor and a CMOS transistor will hereinafter be referred to as a BiCMOS transistor.
Bipolar transistors are classified into vertical transistors and lateral transistors. In a vertical bipolar transistor, carriers flow from an emitter in a vertical direction and reach a collector. Since a collector region is formed in a position deep from a wafer surface, an emitter-collector resistance increases, thus making the transistor disadvantageous for high-speed operation. In addition, the transistor requires a high-concentration buried layer, a collector epitaxial layer, a deep trench isolation, and the like. Consequently, the number of process steps increases, thus increasing costs to increase.
Meanwhile, the lateral bipolar transistor is simpler in structure than the vertical bipolar transistor. In addition, a BiCMOS transistor can be composed by adding a relatively small number of process steps to that of a CMOS transistor. Furthermore, since a collector electrode can be directly brought into contact with a collector region, the lateral bipolar transistor is also advantageous for high-speed operation. Accordingly, in the BiCMOS transistor, it is desirable to apply the lateral bipolar transistor in which carries flow in a lateral direction.
A lateral bipolar transistor is described in, for example, US 2005/0040495 A1 (hereinafter also referred to as Patent Document 1). The lateral NPN transistor described in Patent Document 1 is a transistor called a Horizontal Current Bipolar Transistor (HCBT).